Semiconductor memory devices have a matrix-like arrangement of memory cells in columns and rows which are addressed via word lines running along the rows and bit lines running along the columns. Among a multiplicity of possible memory media, also suitable is a programmable electrical resistance such as is formed, for example, by solid-state ionic memory elements. Memory elements of this type are described, for example, in the publication by R. Symanczyk, et al., “Electrical Characterization of Solid State Ionic Memory Elements”, Non-volatile Memory Technology Symposium 2003. They comprise, e.g., a thin film of a silver-doped chalcogenide or oxide glass as solid electrolyte between a silver anode and a cathode composed of a chemically inert material. If an electrical voltage of suitable polarity is applied to the electrodes, electrons flow from the cathode to the anode and reduce a corresponding number of positive silver ions which emerge from the anode into the chalcogenide or oxide glass. As a result, a deposition composed of silver atoms is formed in the solid electrolyte, the silver atoms reducing the electrical resistance of the material. By applying an electrical voltage of opposite polarity, it is possible to reverse the deposition of the silver atoms in the solid electrolyte, with the result that the silver atoms are oxidized and transported back as ions into the silver anode and the electrical resistance of the material is thereby increased. The programming state—which is defined by the electrical resistance of the solid electrolyte—of a memory cell formed with such a memory element can thus be altered in a simple manner by application of suitable voltages.
In order to read out the content of a memory cell, it is necessary to have a further electrical resistance as a reference quantity, with which the present resistance value of the memory cell can be compared in order to ascertain whether the memory cell is programmed or not programmed. In the case of row-by-row addressing of the memory cells via a word line, however, all the memory cells of the relevant row are addressed, with the result that the bit lines arranged in columns are short-circuited onto the read lines or source lines. In order to be able to use a bit line as a reference bit line, it must not be driven with the same word line with which the memory cell to be read is also addressed, in order that the bit line can be coupled up with a separate reference resistance. In the case of a conventional arrangement of the memory cells in rows and columns with word lines correspondingly arranged in rows and bit lines arranged in columns, no bit line adjacent to a selected bit line can be coupled as the reference bit line. The reference resistance therefore has to be determined by means of a line arranged far away from the selected bit line. A noise level coupled into the lines can become apparent in disturbing fashion in this case. Moreover, additionally required reference bit lines increase the area requirement. Within the memory cell array, however, bit lines are already required for each memory cell present along a word line. The bit lines are usually produced in the second metallization level and determine the minimum structural fineness of the memory cell array.